Invention Grant
- Patent Title: Method of manufacturing a multilayer printed wiring board
- Patent Title (中): 制造多层印刷线路板的方法
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Application No.: US12652255Application Date: 2010-01-05
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Publication No.: US07971354B2Publication Date: 2011-07-05
- Inventor: Takashi Kariya , Toshiki Furutani
- Applicant: Takashi Kariya , Toshiki Furutani
- Applicant Address: JP Ogaki-shi
- Assignee: Ibiden Co., Ltd.
- Current Assignee: Ibiden Co., Ltd.
- Current Assignee Address: JP Ogaki-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2004-023271 20040130; JP2004-139862 20040510
- Main IPC: H05K3/02
- IPC: H05K3/02

Abstract:
A multilayer printed wiring board manufacturing method including forming conductor posts, which are of substantially uniform thickness and with which the top surfaces are protected by a resist, on a conductor pattern disposed on an upper surface of a build-up layer formed on a core substrate, shaping the conductor posts to have a constriction by adjusting the time of immersion in an etching solution that etches the conductor posts, forming a low elastic modulus layer of substantially the same height as the conductor posts after removing the resist at the top surfaces, and forming mounting electrodes on upper surfaces of the conductor posts.
Public/Granted literature
- US20100108637A1 MULTILAYER PRINTED WIRING BOARD AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2010-05-06
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