Invention Grant
US07972521B2 Method of making reliable wafer level chip scale package semiconductor devices
有权
制造可靠的晶圆级芯片级封装半导体器件的方法
- Patent Title: Method of making reliable wafer level chip scale package semiconductor devices
- Patent Title (中): 制造可靠的晶圆级芯片级封装半导体器件的方法
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Application No.: US11685085Application Date: 2007-03-12
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Publication No.: US07972521B2Publication Date: 2011-07-05
- Inventor: Umesh Sharma , Harry Yue Gee , Phillip Gene Holland
- Applicant: Umesh Sharma , Harry Yue Gee , Phillip Gene Holland
- Applicant Address: US AZ Phoenix
- Assignee: Semiconductor Components Industries LLC
- Current Assignee: Semiconductor Components Industries LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Main IPC: H05K3/00
- IPC: H05K3/00
Abstract:
The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.
Public/Granted literature
- US20080227240A1 Method of Making Reliable Wafer Level Chip Scale Package Semiconductor Devices Public/Granted day:2008-09-18
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