Invention Grant
- Patent Title: Semiconductor device having wiring line and manufacturing method thereof
- Patent Title (中): 具有布线的半导体装置及其制造方法
-
Application No.: US12359427Application Date: 2009-01-26
-
Publication No.: US07972903B2Publication Date: 2011-07-05
- Inventor: Hiroyasu Jobetto
- Applicant: Hiroyasu Jobetto
- Applicant Address: JP Tokyo
- Assignee: Casio Computer Co., Ltd.
- Current Assignee: Casio Computer Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz, Goodman & Chick, PC
- Priority: JP2008-020691 20080131
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48
Abstract:
An insulating film covering the lower surface of an external connection electrode of a semiconductor construct is formed. A mask metal layer in which there is formed an opening having a planar size smaller than that of the external connection electrode is formed on the insulating film. The mask metal layer is used as a mask to apply a laser beam to the insulating film, such that a connection opening reaching the external connection electrode is formed in the insulating film. A wiring line is formed on the insulating film in such a manner as to be connected to the external connection electrode via the connection opening.
Public/Granted literature
- US20090194866A1 SEMICONDUCTOR DEVICE HAVING WIRING LINE AND MANUFACTURING METHOD THEREOF Public/Granted day:2009-08-06
Information query
IPC分类:
