Invention Grant
- Patent Title: Semiconductor die package including exposed connections
- Patent Title (中): 半导体管芯封装包括裸露的连接
-
Application No.: US12044314Application Date: 2008-03-07
-
Publication No.: US07972906B2Publication Date: 2011-07-05
- Inventor: Erwin Victor R. Cruz , Maria Cristina B. Estacio
- Applicant: Erwin Victor R. Cruz , Maria Cristina B. Estacio
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a clip structure. Slots are formed within the molding material covering portions of the semiconductor die package. The slots are located between a first portion and the second portion of the clip structure, and the slot overlap with the semiconductor die.
Public/Granted literature
- US20090224383A1 SEMICONDUCTOR DIE PACKAGE INCLUDING EXPOSED CONNECTIONS Public/Granted day:2009-09-10
Information query
IPC分类:
