Invention Grant
- Patent Title: Purge step-controlled sequence of processing semiconductor wafers
- Patent Title (中): 冲洗半导体晶片的步进控制序列
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Application No.: US12248741Application Date: 2008-10-09
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Publication No.: US07972961B2Publication Date: 2011-07-05
- Inventor: Toru Sugiyama , Ryu Nakano
- Applicant: Toru Sugiyama , Ryu Nakano
- Applicant Address: JP Tokyo
- Assignee: ASM Japan K.K.
- Current Assignee: ASM Japan K.K.
- Current Assignee Address: JP Tokyo
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/20 ; C23C16/00

Abstract:
A method of processing semiconductor substrates includes: depositing a film on a substrate in a reaction chamber; evacuating the reaction chamber without purging the reaction chamber; opening a gate valve and replacing the substrate with a next substrate via the transfer chamber wherein the pressure of the transfer chamber is controlled to be higher than that of the reaction chamber before and while the gate valve is opened; repeating the above steps and removing the substrate from the reaction chamber; and purging and evacuating the reaction chamber, and cleaning the reaction chamber with a cleaning gas.
Public/Granted literature
- US20100093181A1 PURGE STEP-CONTROLLED SEQUENCE OF PROCESSING SEMICONDUCTOR WAFERS Public/Granted day:2010-04-15
Information query
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