Invention Grant
US07973309B2 TEG pattern for detecting void in device isolation layer and method of forming the same
失效
用于检测器件隔离层中空隙的TEG图案及其形成方法
- Patent Title: TEG pattern for detecting void in device isolation layer and method of forming the same
- Patent Title (中): 用于检测器件隔离层中空隙的TEG图案及其形成方法
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Application No.: US12435161Application Date: 2009-05-04
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Publication No.: US07973309B2Publication Date: 2011-07-05
- Inventor: Tae-Gyun Kim , Dong-Suk Shin , Joo-Won Lee , Ha-Jin Lim
- Applicant: Tae-Gyun Kim , Dong-Suk Shin , Joo-Won Lee , Ha-Jin Lim
- Applicant Address: KR Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR10-2008-0045074 20080515
- Main IPC: H01L23/544
- IPC: H01L23/544

Abstract:
Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.
Public/Granted literature
- US20090283764A1 TEG PATTERN FOR DETECTING VOID IN DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME Public/Granted day:2009-11-19
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