Invention Grant
- Patent Title: Semiconductor package structure and method for manufacturing the same
- Patent Title (中): 半导体封装结构及其制造方法
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Application No.: US12501100Application Date: 2009-07-10
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Publication No.: US07973310B2Publication Date: 2011-07-05
- Inventor: David Wei Wang , An-Hong Liu , Hao-Yin Tsai , Hsiang-Ming Huang , Yi-Chang Lee , Shu-Ching Ho
- Applicant: David Wei Wang , An-Hong Liu , Hao-Yin Tsai , Hsiang-Ming Huang , Yi-Chang Lee , Shu-Ching Ho
- Applicant Address: TW Hsinchu
- Assignee: Chipmos Technologies Inc.
- Current Assignee: Chipmos Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, PLLC
- Priority: TW98100219A 20090106
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.
Public/Granted literature
- US20100007001A1 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2010-01-14
Information query
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