Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, the piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.