Invention Grant
- Patent Title: High breakdown voltage semiconductor device and fabrication method of the same
- Patent Title (中): 高击穿电压半导体器件及其制造方法
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Application No.: US11362116Application Date: 2006-02-27
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Publication No.: US07973361B2Publication Date: 2011-07-05
- Inventor: Yoshinobu Sato , Hiroyoshi Ogura , Hisao Ichijo , Teruhisa Ikuta , Toru Terashita
- Applicant: Yoshinobu Sato , Hiroyoshi Ogura , Hisao Ichijo , Teruhisa Ikuta , Toru Terashita
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-098896 20050330
- Main IPC: H01L31/113
- IPC: H01L31/113

Abstract:
A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.
Public/Granted literature
- US20060220130A1 High breakdown voltage semiconductor device and fabrication method of the same Public/Granted day:2006-10-05
Information query
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