Invention Grant
- Patent Title: Fully depleted silicon-on-insulator CMOS logic
- Patent Title (中): 完全耗尽的绝缘体上硅CMOS逻辑
-
Application No.: US11391087Application Date: 2006-03-28
-
Publication No.: US07973370B2Publication Date: 2011-07-05
- Inventor: Leonard Forbes
- Applicant: Leonard Forbes
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: H01L31/119
- IPC: H01L31/119
Abstract:
A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.
Public/Granted literature
- US20060170050A1 Fully depleted silicon-on-insulator CMOS logic Public/Granted day:2006-08-03
Information query
IPC分类:
