Invention Grant
- Patent Title: Isolated tri-gate transistor fabricated on bulk substrate
- Patent Title (中): 在本体衬底上制造的隔离三栅极晶体管
-
Application No.: US12590562Application Date: 2009-11-10
-
Publication No.: US07973389B2Publication Date: 2011-07-05
- Inventor: Rafael Rios , Jack Kavalieros , Stephen M. Cea
- Applicant: Rafael Rios , Jack Kavalieros , Stephen M. Cea
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Rahul D. Engineer
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/06 ; H01L29/41

Abstract:
A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
Public/Granted literature
- US20100059821A1 Isolated tri-gate transistor fabricated on bulk substrate Public/Granted day:2010-03-11
Information query
IPC分类: