Invention Grant
US07973414B2 Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same 有权
适用于堆叠半导体封装的半导体封装通孔和具有该半导体封装的半导体封装

  • Patent Title: Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same
  • Patent Title (中): 适用于堆叠半导体封装的半导体封装通孔和具有该半导体封装的半导体封装
  • Application No.: US11856149
    Application Date: 2007-09-17
  • Publication No.: US07973414B2
    Publication Date: 2011-07-05
  • Inventor: Min Suk Suh
  • Applicant: Min Suk Suh
  • Applicant Address: KR Kyoungki-do
  • Assignee: Hynix Semiconductor Inc.
  • Current Assignee: Hynix Semiconductor Inc.
  • Current Assignee Address: KR Kyoungki-do
  • Agency: Ladas & Parry LLP
  • Priority: KR10-2007-0082437 20070816
  • Main IPC: H01L23/48
  • IPC: H01L23/48 H01L23/52 H01L29/40
Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same
Abstract:
A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.
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