Invention Grant
- Patent Title: Manufacturing process and structure of through silicon via
- Patent Title (中): 通过硅通孔的制造工艺和结构
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Application No.: US12133828Application Date: 2008-06-05
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Publication No.: US07973415B2Publication Date: 2011-07-05
- Inventor: Michihiro Kawashita , Yasuhiro Yoshimura , Naotaka Tanaka , Takahiro Naito , Takashi Akazawa
- Applicant: Michihiro Kawashita , Yasuhiro Yoshimura , Naotaka Tanaka , Takahiro Naito , Takashi Akazawa
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Mattingly & Malur, PC
- Priority: JP2007-150289 20070606
- Main IPC: H01L29/41
- IPC: H01L29/41
Abstract:
A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.
Public/Granted literature
- US20090014843A1 MANUFACTURING PROCESS AND STRUCTURE OF THROUGH SILICON VIA Public/Granted day:2009-01-15
Information query
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