Invention Grant
- Patent Title: Integrated circuit with delay selecting input selection circuitry
- Patent Title (中): 具有延迟选择输入选择电路的集成电路
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Application No.: US12637745Application Date: 2009-12-14
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Publication No.: US07973558B2Publication Date: 2011-07-05
- Inventor: Brad Hutchings , Jason Redgrave
- Applicant: Brad Hutchings , Jason Redgrave
- Applicant Address: US CA Santa Clara
- Assignee: Tabula, Inc.
- Current Assignee: Tabula, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Adeli & Tollen LLP
- Main IPC: H03K19/173
- IPC: H03K19/173

Abstract:
Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit.
Public/Granted literature
- US20100156456A1 Integrated Circuit with Delay Selecting Input Selection Circuitry Public/Granted day:2010-06-24
Information query
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