An output buffer including a first input stage circuit, a first output stage circuit, a second output stage circuit, a first switching module, and a second switching module is disclosed. The first output stage circuit is coupled to a first data line. The second output stage circuit is coupled to a second data line. The first switching module is coupled between the first input stage circuit and the first output stage circuit. The second switching module is coupled between the first input stage circuit and the second output stage circuit.