Invention Grant
- Patent Title: Systems and methods for synchronous, retimed analog to digital conversion
- Patent Title (中): 用于基于锁存的模数转换的系统和方法
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Application No.: US12669482Application Date: 2008-06-06
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Publication No.: US07973692B2Publication Date: 2011-07-05
- Inventor: Erik Chmelar , Choshu Ito , William Loh
- Applicant: Erik Chmelar , Choshu Ito , William Loh
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Hamilton DeSanctis & Cha
- International Application: PCT/US2008/066074 WO 20080606
- International Announcement: WO2009/148458 WO 20091210
- Main IPC: H03M1/36
- IPC: H03M1/36

Abstract:
Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.
Public/Granted literature
- US20100195776A1 Systems and Methods for Synchronous, Retimed Analog to Digital Conversion Public/Granted day:2010-08-05
Information query
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