Invention Grant
US07974127B2 Operation methods for memory cell and array for reducing punch through leakage
有权
用于减少穿孔渗漏的存储单元和阵列的操作方法
- Patent Title: Operation methods for memory cell and array for reducing punch through leakage
- Patent Title (中): 用于减少穿孔渗漏的存储单元和阵列的操作方法
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Application No.: US12264886Application Date: 2008-11-04
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Publication No.: US07974127B2Publication Date: 2011-07-05
- Inventor: Lit-Ho Chong , Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
- Applicant: Lit-Ho Chong , Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Kilpatrick Townsend and Stockton LLP
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
Public/Granted literature
- US20090116286A1 OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE Public/Granted day:2009-05-07
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