The processor according to the present invention is a processor having a forwarding function and includes an attribute information holding unit (141) that holds attribute information regarding inhibition of writing to a register and a register write inhibition circuit (126) that holds, when forwarding is performed, the writing of the data forwarded according to attribute information. The attribute information holding unit (141) holds the attribute information by relating the attribute information to at least one register. Alternatively, the attribute information holding unit is a part of plural pipeline buffers and passes the attribute information along with the data to be forwarded, to a pipeline buffer in a subsequent stage.