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US07975197B2 On-chip scan clock generator for ASIC testing 失效
用于ASIC测试的片上扫描时钟发生器

On-chip scan clock generator for ASIC testing
Abstract:
A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence of nonconcurrent scan clock signals at separate outputs respectively in response to a first state of the scan shift mode signal.
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