Invention Grant
- Patent Title: Power supply noise analysis model generating method and power supply noise analysis model generating apparatus
- Patent Title (中): 电源噪声分析模型生成方法和电源噪声分析模型生成装置
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Application No.: US11864122Application Date: 2007-09-28
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Publication No.: US07975253B2Publication Date: 2011-07-05
- Inventor: Yoshiyuki Iwakura , Shogo Fujimori , Tendou Hirai , Hitoshi Chida , Kazuyoshi Kanei , Koutarou Nimura
- Applicant: Yoshiyuki Iwakura , Shogo Fujimori , Tendou Hirai , Hitoshi Chida , Kazuyoshi Kanei , Koutarou Nimura
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2006-352084 20061227
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.
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