Invention Grant
US07985624B2 Method of manufacturing semiconductor device having plural dicing steps
失效
具有多个切割步骤的半导体器件的制造方法
- Patent Title: Method of manufacturing semiconductor device having plural dicing steps
- Patent Title (中): 具有多个切割步骤的半导体器件的制造方法
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Application No.: US12203189Application Date: 2008-09-03
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Publication No.: US07985624B2Publication Date: 2011-07-26
- Inventor: Yoshiharu Kaneda
- Applicant: Yoshiharu Kaneda
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2007-227569 20070903
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/28
Abstract:
Provided is a method of manufacturing a semiconductor device including: arranging multiple dies planarly between a first lead frame plate and a second lead frame plate, which face each other, to connect the multiple semiconductor chips to each of the first lead frame plate and the second lead frame plate; filling a resin between the first lead frame plate and the second lead frame plate to seal the multiple dies; performing a first dicing on a laminated body including the first lead frame plate, the resin, and the second lead frame plate, between the adjacent dies, to separate at least the first lead frame plate by cutting; applying plating to the laminated body with at least the first lead frame plate being separated by cutting; and performing a second dicing on a remainder of the laminated body between the adjacent dies, to separate the laminated body into individual semiconductor devices.
Public/Granted literature
- US20090057851A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2009-03-05
Information query
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