Invention Grant
- Patent Title: Method for patterning semiconductor device having magnetic tunneling junction structure
- Patent Title (中): 具有磁性隧道结结构的半导体器件图形化方法
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Application No.: US12492697Application Date: 2009-06-26
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Publication No.: US07985667B2Publication Date: 2011-07-26
- Inventor: Sang-Hoon Cho
- Applicant: Sang-Hoon Cho
- Applicant Address: KR Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2008-0086308 20080902
- Main IPC: H01L21/22
- IPC: H01L21/22 ; H01L21/38

Abstract:
A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.
Public/Granted literature
- US20100055804A1 METHOD FOR PATTERNING SEMICONDUCTOR DEVICE HAVING MAGNETIC TUNNELING JUNCTION STRUCTURE Public/Granted day:2010-03-04
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