Invention Grant
- Patent Title: Method of manufacturing a semiconductor integrated circuit device
- Patent Title (中): 制造半导体集成电路器件的方法
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Application No.: US12896933Application Date: 2010-10-04
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Publication No.: US07985678B2Publication Date: 2011-07-26
- Inventor: Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
- Applicant: Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2003-153882 20030530
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
Public/Granted literature
- US20110021022A1 METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2011-01-27
Information query
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