Invention Grant
- Patent Title: Wafer level package and method of fabricating the same
- Patent Title (中): 晶圆级封装及其制造方法
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Application No.: US12208512Application Date: 2008-09-11
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Publication No.: US07985697B2Publication Date: 2011-07-26
- Inventor: Jong Tae Moon , Yong Sung Eom , Min Ji Lee , Hyun Kyu Yu
- Applicant: Jong Tae Moon , Yong Sung Eom , Min Ji Lee , Hyun Kyu Yu
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Agency: Rabin & Berdo, P.C.
- Priority: KR10-2008-0035488 20080417
- Main IPC: H01L21/31
- IPC: H01L21/31

Abstract:
Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.
Public/Granted literature
- US20090261481A1 WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME Public/Granted day:2009-10-22
Information query
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