Invention Grant
- Patent Title: Semiconductor device and method of manufacture thereof
- Patent Title (中): 半导体装置及其制造方法
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Application No.: US11802668Application Date: 2007-05-24
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Publication No.: US07986004B2Publication Date: 2011-07-26
- Inventor: Akira Ohdaira , Hisaji Nishimura , Hiroyoshi Ogura
- Applicant: Akira Ohdaira , Hisaji Nishimura , Hiroyoshi Ogura
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Steptoe & Johnson LLP
- Priority: JP2006-170795 20060621
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
In a high withstand voltage transistor of a LOCOS offset drain type having a buried layer, a plurality of stripe-shaped diffusion layers are formed below a diffusion layer ranging from an offset layer to a drain layer and a portion between the drain region and the buried layer is depleted completely; thus, a withstand voltage between the drain region and the buried layer is improved. By the formation of the stripe-shaped diffusion layers, the drain region becomes widened; thus, on-resistance is reduced. Further, the buried layer is made high in concentration so as to sufficiently suppress an operation of a parasitic bipolar transistor.
Public/Granted literature
- US20070296046A1 Semiconductor device and method of manufacture thereof Public/Granted day:2007-12-27
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