Invention Grant
- Patent Title: MOS transistor and manufacturing method thereof
- Patent Title (中): MOS晶体管及其制造方法
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Application No.: US12056293Application Date: 2008-03-27
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Publication No.: US07986007B2Publication Date: 2011-07-26
- Inventor: Kai-Yi Huang , Ta-Hsun Yeh , Yuh-Sheng Jean
- Applicant: Kai-Yi Huang , Ta-Hsun Yeh , Yuh-Sheng Jean
- Applicant Address: TW Hsinchu
- Assignee: Realtek Semiconductor Corp.
- Current Assignee: Realtek Semiconductor Corp.
- Current Assignee Address: TW Hsinchu
- Agency: Thomas, Kayden, Horstemeyer & Risley, LLP
- Priority: TW96112832A 20070412
- Main IPC: H01L27/12
- IPC: H01L27/12

Abstract:
The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required.
Public/Granted literature
- US20080251841A1 MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF Public/Granted day:2008-10-16
Information query
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