Invention Grant
- Patent Title: Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production
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Application No.: US12511845Application Date: 2009-07-29
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Publication No.: US07986009B2Publication Date: 2011-07-26
- Inventor: Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
- Applicant: Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Main IPC: H01L23/62
- IPC: H01L23/62
Abstract:
A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.
Public/Granted literature
- US08076728B2 Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production Public/Granted day:2011-12-13
Information query
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