Invention Grant
- Patent Title: Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices
- Patent Title (中): 用于调整可编程逻辑器件的性能特性和功耗的装置和方法
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Application No.: US11420737Application Date: 2006-05-27
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Publication No.: US07986160B2Publication Date: 2011-07-26
- Inventor: Tim Tri Hoang , Sergey Shumarayev
- Applicant: Tim Tri Hoang , Sergey Shumarayev
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Law Offices of Maximilian R. Peterson
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K19/173
Abstract:
A PLD includes at least one IP block or circuit, and at least one I/O block or circuit. The performance of the at least one IP block is adjusted in order to meet at least one performance characteristic by changing a supply level of the at least one IP block, by adjusting at least one body bias level of the IP block, or both. The performance of the at least one I/O block is adjusted by changing a supply level of the at least one I/O block, by adjusting at least one body bias level of the I/O block, or both.
Public/Granted literature
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