Invention Grant
- Patent Title: Interface circuit
- Patent Title (中): 接口电路
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Application No.: US12794434Application Date: 2010-06-04
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Publication No.: US07986162B2Publication Date: 2011-07-26
- Inventor: Tatsuya Ueno
- Applicant: Tatsuya Ueno
- Applicant Address: JP Tokyo
- Assignee: Yamatake Corporation
- Current Assignee: Yamatake Corporation
- Current Assignee Address: JP Tokyo
- Agency: Amster, Rothstein & Ebenstein LLP
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K19/003

Abstract:
An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.
Public/Granted literature
- US20110133779A1 INTERFACE CIRCUIT Public/Granted day:2011-06-09
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