Invention Grant
US07986543B2 Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom
有权
在三维结构中的高速缓存层级的级别之间实现非常高的带宽的方法以及由此产生的三维结构
- Patent Title: Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom
- Patent Title (中): 在三维结构中的高速缓存层级的级别之间实现非常高的带宽的方法以及由此产生的三维结构
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Application No.: US12116771Application Date: 2008-05-07
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Publication No.: US07986543B2Publication Date: 2011-07-26
- Inventor: Philip George Emma
- Applicant: Philip George Emma
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: McGinn Intellectual Property Law Group, PLLC
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.
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