Invention Grant
- Patent Title: SRAM cell with read buffer controlled for low leakage current
- Patent Title (中): 具有读缓冲器的SRAM单元控制低漏电流
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Application No.: US12416857Application Date: 2009-04-01
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Publication No.: US07986566B2Publication Date: 2011-07-26
- Inventor: Theodore W. Houston
- Applicant: Theodore W. Houston
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G11C7/10
- IPC: G11C7/10
Abstract:
A functional memory of the integrated circuit includes row and column periphery units and an array of memory cells having a core storage element and a read buffer. The functional memory further includes a read buffer supply line that is connected to the read buffer, wherein the read buffer supply line is switchable between an operating mode output and a low-power mode output of a read buffer supply that is separate from core storage element supplies.
Public/Granted literature
- US20100254199A1 SRAM CELL WITH READ BUFFER CONTROLLED FOR LOW LEAKAGE CURRENT Public/Granted day:2010-10-07
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