Invention Grant
US07986573B2 Programming memory with direct bit line driving to reduce channel-to-floating gate coupling
有权
使用直接位线驱动来编程存储器,以减少通道到浮置栅极耦合
- Patent Title: Programming memory with direct bit line driving to reduce channel-to-floating gate coupling
- Patent Title (中): 使用直接位线驱动来编程存储器,以减少通道到浮置栅极耦合
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Application No.: US12624602Application Date: 2009-11-24
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Publication No.: US07986573B2Publication Date: 2011-07-26
- Inventor: Yan Li
- Applicant: Yan Li
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies Inc.
- Current Assignee: SanDisk Technologies Inc.
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus & DeNiro LLP
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines. Dedicated power supplies can be used to provide the step up to avoid a risk that the unselected bit lines begin floating due to pre-charging of other bit lines The selected bit lines are coupled higher as a function of their proximity to unselected bit lines, and in preparation for applying a program pulse. Coupling may be used for slow and fast programming modes. A dedicated power supply can be provided for driving slow programming mode bit lines at a level which provides coupling compensation.
Public/Granted literature
- US20110122703A1 PROGRAMMING MEMORY WITH DIRECT BIT LINE DRIVING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING Public/Granted day:2011-05-26
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