Invention Grant
US07986576B2 Digit line equilibration using access devices at the edge of sub-arrays
有权
使用子阵列边缘的接入设备进行数字线路平衡
- Patent Title: Digit line equilibration using access devices at the edge of sub-arrays
- Patent Title (中): 使用子阵列边缘的接入设备进行数字线路平衡
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Application No.: US12870425Application Date: 2010-08-27
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Publication No.: US07986576B2Publication Date: 2011-07-26
- Inventor: Werner Juengling
- Applicant: Werner Juengling
- Applicant Address: US ID Boise
- Assignee: Micron Technoloy, Inc.
- Current Assignee: Micron Technoloy, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other.
Public/Granted literature
- US20100322025A1 DIGIT LINE EQUILIBRATION USING ACCESS DEVICES AT THE EDGE OF SUB-ARRAYS Public/Granted day:2010-12-23
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