An apparatus including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to a modulated signal and a seed value selected in response to a first control signal. The second circuit may be configured to generate a second control signal in response to the demodulated signal. The third circuit may be configured to generate the first control signal in response to the second control signal, a compensation signal, and the first control signal, where generation of the first control signal includes adding the second control signal, the compensation signal, and a latched version of the first control signal. Generation of the latched version of the first control signal may include sampling the first control signal in response to a clock signal. The compensation signal may compensate for variation in the clock signal.