Invention Grant
US07987062B2 Delay circuit, test apparatus, storage medium semiconductor chip, initializing circuit and initializing method
失效
延迟电路,测试装置,存储介质半导体芯片,初始化电路和初始化方法
- Patent Title: Delay circuit, test apparatus, storage medium semiconductor chip, initializing circuit and initializing method
- Patent Title (中): 延迟电路,测试装置,存储介质半导体芯片,初始化电路和初始化方法
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Application No.: US11763448Application Date: 2007-06-15
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Publication No.: US07987062B2Publication Date: 2011-07-26
- Inventor: Kazuhiro Fujita , Masakatsu Suda , Takuya Hasumi
- Applicant: Kazuhiro Fujita , Masakatsu Suda , Takuya Hasumi
- Applicant Address: JP Tokyo
- Assignee: Advantest Corporation
- Current Assignee: Advantest Corporation
- Current Assignee Address: JP Tokyo
- Agency: Osha Liang LLP
- Priority: JP2006-226478 20060823
- Main IPC: G01R29/02
- IPC: G01R29/02

Abstract:
A delay circuit includes a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value. The initializing section includes a first loop path that inputs an output signal of the first delay element into the first delay element and a second loop path that inputs an output signal of the second delay element into the second delay element. The initialization section includes a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element, a second measuring section that measures a delay amount in the second delay element, and a delay amount computing section that corrects a delay amount measured by the first measuring section.
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