Invention Grant
US07987222B1 Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension
有权
用于实现利用数字信号处理器块存储器扩展的乘法器的方法和装置
- Patent Title: Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension
- Patent Title (中): 用于实现利用数字信号处理器块存储器扩展的乘法器的方法和装置
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Application No.: US10829559Application Date: 2004-04-22
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Publication No.: US07987222B1Publication Date: 2011-07-26
- Inventor: Asher Hazanchuk , Benjamin Esposito
- Applicant: Asher Hazanchuk , Benjamin Esposito
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agent L. Cho
- Main IPC: G06F7/38
- IPC: G06F7/38
Abstract:
A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a second plurality of bits from the first number and a second plurality of bits from the second number is retrieved. The product is scaled with respect to a position of the first plurality of bits from the first number and a position of the first plurality of bits from the second number. The stored value is scaled with respect to a position of the second plurality of bits from the second number and a position of the second plurality of bits from the second number. The scaled product and the scaled stored value are summed.
Information query
