Invention Grant
- Patent Title: Interrupt coalescing control scheme
- Patent Title (中): 中断合并控制方案
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Application No.: US11525738Application Date: 2006-09-22
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Publication No.: US07987307B2Publication Date: 2011-07-26
- Inventor: Parthasarathy Sarangam , Anil Vasudevan
- Applicant: Parthasarathy Sarangam , Anil Vasudevan
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F13/24
- IPC: G06F13/24 ; G06F13/32

Abstract:
In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.
Public/Granted literature
- US20080077724A1 Interrupt coalescing control scheme Public/Granted day:2008-03-27
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