Invention Grant
US07987342B1 Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
有权
具有解码器，基本块高速缓存，多块缓存和定序器的跟踪单元
- Patent Title: Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
- Patent Title (中): 具有解码器，基本块高速缓存，多块缓存和定序器的跟踪单元
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Application No.: US11880862Application Date: 2007-07-23
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Publication No.: US07987342B1Publication Date: 2011-07-26
- Inventor: Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
- Applicant: Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
- Applicant Address: US CA Redwood City
- Assignee: Oracle America, Inc.
- Current Assignee: Oracle America, Inc.
- Current Assignee Address: US CA Redwood City
- Agency: Osha • Liang LLP
- Main IPC: G06F9/30
- IPC: G06F9/30
Abstract:
An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor. The instruction processing circuit includes a cache circuit operable to store a second type of sequence of operations that represents at least a portion of a first type of sequence of operations, where the sequence of operations of the second type includes at most one control transfer that, when present, ends a first portion of a sequence of instructions, where the cache circuit is further configured to store a third type of sequence of operations that represents a set of at least two sequences of operations.
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