A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting controller configured to receive the first test control signal and the second test control signal to output a shifting control signal in response to the selection end signal; and a pattern test signal generator configured to select a stress pattern corresponding to the pattern selection signals to generate a plurality of test mode signals for controlling a sequential entry into a plurality of test modes for executing the stress pattern in response to the shifting control signal.