Invention Grant
- Patent Title: Pattern verification method, program thereof, and manufacturing method of semiconductor device
- Patent Title (中): 模式验证方法，程序以及半导体器件的制造方法
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Application No.: US12585073Application Date: 2009-09-02
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Publication No.: US07987435B2Publication Date: 2011-07-26
- Inventor: Ryuji Ogawa , Koji Hashimoto
- Applicant: Ryuji Ogawa , Koji Hashimoto
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-244448 20050825
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.
Public/Granted literature
- US20100031224A1 Pattern verification method, program thereof, and manufacturing method of semiconductor device Public/Granted day:2010-02-04
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