Invention Grant
- Patent Title: Clocking architecture in stacked and bonded dice
- Patent Title (中): 时钟结构在堆叠和保税骰子
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Application No.: US12953202Application Date: 2010-11-23
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Publication No.: US07989226B2Publication Date: 2011-08-02
- Inventor: Mark Shane Peng
- Applicant: Mark Shane Peng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network.
Public/Granted literature
- US20110102044A1 Clocking Architecture in Stacked and Bonded Dice Public/Granted day:2011-05-05
Information query
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