Invention Grant
- Patent Title: DRAM cell transistor device and method
- Patent Title (中): DRAM单元晶体管器件及方法
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Application No.: US12238521Application Date: 2008-09-26
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Publication No.: US07989284B2Publication Date: 2011-08-02
- Inventor: JoBong Choi
- Applicant: JoBong Choi
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Kilpatrick Townsend and Stockton LLP
- Priority: CN200710094551 20071213
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L21/8242

Abstract:
A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing a portion of the photo resist to expose the protective layer overlying a first region while maintaining the photo resist overlying a second region. The method includes implanting impurities for threshold voltage adjustment into the first region while the second region is substantially free of the impurities for threshold voltage adjustment. The method also includes forming a source region and a drain region. The method further includes providing a conductive structure over the source region. A junction between the conductive structure and the source region is substantially within the second region. The method then provides a storage capacitor in electrical contact with the source region via the conductive structure.
Public/Granted literature
- US20090152608A1 DRAM Cell Transistor Device and Method Public/Granted day:2009-06-18
Information query
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