Invention Grant
- Patent Title: Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
- Patent Title (中): 在半导体结构中形成隔离的有源区，沟槽和导电线的方法以及包括其的半导体结构
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Application No.: US12114932Application Date: 2008-05-05
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Publication No.: US07989307B2Publication Date: 2011-08-02
- Inventor: Kunal R. Parekh , John K. Zahurak
- Applicant: Kunal R. Parekh , John K. Zahurak
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.
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