Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry

Invention Grant

US07989336B2 Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry 有权

Title translation: 在集成电路的制造中形成多条导线的方法，形成导线阵列的方法和集成电路

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Patent Title: Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry
Patent Title (中): 在集成电路的制造中形成多条导线的方法，形成导线阵列的方法和集成电路
Application No.: US12436262

Application Date: 2009-05-06
Publication No.: US07989336B2

Publication Date: 2011-08-02
Inventor: Sanh Tang , Ming Zhang
Applicant: Sanh Tang , Ming Zhang
Applicant Address: US ID Boise
Assignee: Micron Technology, Inc.
Current Assignee: Micron Technology, Inc.
Current Assignee Address: US ID Boise
Agency: Wells St. John P.S.
Main IPC: H01L21/4763
IPC: H01L21/4763 ; H01L21/76 ; H01L21/336

Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry

Abstract:

A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated.

Abstract(Chinese):

在集成电路的制造中形成一对导线的方法包括将沟槽形成为接纳在衬底上的镶嵌材料。导电材料沉积在镶嵌材料上并且在沟槽内沉积以覆盖沟槽。导电材料至少被去除到镶嵌材料，以留下留在沟槽中的至少一些导电材料。蚀刻通过沟槽内的导电材料纵向导电，以在沟槽内形成第一和第二导电线，该沟槽中的第一和第二导电线沿着第一和第二导电线的至少大部分长度在横截面上相互镜像。考虑其他实现。

Public/Granted literature

US20100283155A1 Methods Of Forming A Plurality Of Conductive Lines In The Fabrication Of Integrated Circuitry, Methods Of Forming An Array Of Conductive Lines, And Integrated Circuitry Public/Granted day:2010-11-11

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）