Invention Grant
- Patent Title: Manufacturing method for semiconductor chips and semiconductor wafer
- Patent Title (中): 半导体芯片和半导体晶片的制造方法
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Application No.: US11792815Application Date: 2006-01-10
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Publication No.: US07989803B2Publication Date: 2011-08-02
- Inventor: Kiyoshi Arita , Teruaki Nishinaka
- Applicant: Kiyoshi Arita , Teruaki Nishinaka
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack L.L.P.
- Priority: JP2005-004860 20050112
- International Application: PCT/JP2006/000409 WO 20060110
- International Announcement: WO2006/075725 WO 20060720
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
In a semiconductor wafer that has semiconductor devices arranged in a plurality of device-formation-regions and a TEG placed in dividing regions that define the device-formation-regions, a TEG-placement portion is arranged in the dividing regions partially expanded in width, and the TEG is placed in the TEG-placement portion. Additionally, a protective sheet is stuck to the semiconductor wafer, then plasma etching is performed, and the TEG is removed in a state where it remains in the dividing region and stuck to the protective sheet together with the protective sheet by peeling off the protective sheet, thereby the device-formation-regions are divided into individual pieces, and the semiconductor chips are manufactured.
Public/Granted literature
- US20080128694A1 Manufacturing Method For Semiconductor Chips And Semiconductor Wafer Public/Granted day:2008-06-05
Information query
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