Invention Grant
US07989853B2 Integration of high voltage JFET in linear bipolar CMOS process
有权
在线性双极CMOS工艺中集成高电压JFET
- Patent Title: Integration of high voltage JFET in linear bipolar CMOS process
- Patent Title (中): 在线性双极CMOS工艺中集成高电压JFET
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Application No.: US12537589Application Date: 2009-08-07
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Publication No.: US07989853B2Publication Date: 2011-08-02
- Inventor: Pinghai Hao , Sameer Pendharkar , Philip L. Hower , Marie Denison
- Applicant: Pinghai Hao , Sameer Pendharkar , Philip L. Hower , Marie Denison
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/337
Abstract:
A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.
Public/Granted literature
- US20100032729A1 INTEGRATION OF HIGH VOLTAGE JFET IN LINEAR BIPOLAR CMOS PROCESS Public/Granted day:2010-02-11
Information query
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