Invention Grant
- Patent Title: Capacitive sensing with combinatorial sensor layout
- Patent Title (中): 组合传感器布局的电容传感
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Application No.: US12471206Application Date: 2009-05-22
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Publication No.: US07990160B2Publication Date: 2011-08-02
- Inventor: Joseph K Reynolds
- Applicant: Joseph K Reynolds
- Applicant Address: US CA Santa Clara
- Assignee: Synaptics Incorporated
- Current Assignee: Synaptics Incorporated
- Current Assignee Address: US CA Santa Clara
- Main IPC: G01R27/26
- IPC: G01R27/26

Abstract:
In a method for determining capacitance, a set of sensor electrodes is employed. The set of sensor electrodes comprises at least three sensor electrodes including first, second, and third sensor electrodes. The first sensor electrode meets the second sensor electrode at a first activation region of a plurality of activation regions. The first sensor electrode meets the third sensor at a second activation region of the plurality of activation regions. The second sensor electrode meets the third sensor electrode at a third activation region of the plurality of activation regions. The third sensor electrode transmits while first indicia are received with the first and the second sensor electrodes. The first sensor electrode transmits while second indicia are received with the second sensor electrode. Capacitances associated with the first, second and third activation regions are determined using at least the first indicia and second indicia.
Public/Granted literature
- US20100295564A1 CAPACITIVE SENSING WITH COMBINATORIAL SENSOR LAYOUT Public/Granted day:2010-11-25
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