A circuit for handling single event upsets includes a plurality of digital clock manager circuits. A plurality of counters are respectively coupled by their inputs to the outputs of the digital clock managers and a reset controller is coupled to the outputs of the counters. The reset controller is configured to determine an expected value of the counters. In response to an output value of one of the counters being less than the expected value, the reset controller triggers a reset of the digital clock manager coupled to the input of the one of the counters. In response to an output value of one of the counters being greater than or equal to the expected value, the reset controller continues operation without triggering a reset of a digital clock manager.