A clock correction circuit includes a delay locked loop (DLL) configured to delay an external clock signal and to generate an internal clock signal, a first duty cycle correction (DCC) unit configured to correct a duty cycle of the external clock signal in response to a first duty cycle code, a second DCC unit configured to correct a duty cycle of the internal clock signal in response to a second duty cycle code, and a duty cycle code generation unit configured to select an output of from outputs of the first and second DCC Units and to generate the first and second duty cycle codes by detecting a duty cycle ratio of the selected output.