An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.